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mt9v024: 1/3-inch wide-vga digital image sensor features mt9v024_dsrev. g pub. 4/15 en 1 ?semiconductor components industries, llc, 2015 1/3-inch wide-vga cmos digital image sensor mt9v024 datasheet, rev. g for the latest datasheet revision, please visit www.onsemi.com features ? array format: wide-vga, active 752h x 480v (360,960 pixels) ? global shutter photodiode pixels; simultaneous integration and readout ? rgb bayer, monochrome, or rccc: nir enhanced performance for use with non-visible nir illumination ? readout modes: progressive or interlaced ? shutter efficiency: >99% ? simple two-wire serial interface ? real-time exposure context switching - dual register set ? register lock capability ? window size: user programmable to any smaller format (qvga, cif, qcif). data rate can be maintained independent of window size ? binning: 2 x 2 and 4 x 4 of the full resolution ? adc: on-chip, 10-bit column-parallel (option to operate in 12-bit to 10-bit companding mode) ? automatic controls: auto exposure control (aec) and auto gain control (agc); variable regional and variable weight aec/agc ? support for four unique seri al control register ids to control multiple imagers on the same bus ? data output formats: ? single sensor mode: 10-bit parallel/stand-alone 8-bit or 10-bit serial lvds ? stereo sensor mode: interspersed 8-bit serial lvds ? high dynamic range (hdr) mode applications ? automotive ? unattended surveillance ? stereo vision ?smart vision ?automation ?video as input ?machine vision table 1: key performance parameters parameter value optical format 1/3-inch active imager size 4.51 mm (h) x 2.88 mm (v) 5.35 mm diagonal active pixels 752h x 480v pixel size 6.0 ? mx 6.0 ? m color filter array monochrome, color rgb bayer or rccc pattern shutter type global shutter maximum data rate master clock 27 mp/s 27 mhz full resolution 752 x 480 frame rate 60 fps (at full resolution) adc resolution 10-bit column-parallel responsivity 4.8 v/lux-sec (550 nm) dynamic range >55 db linear; >100 db in hdr mode supply voltage 3.3 v + 0.3 v ?? all supplies) power consumption <160 mw at maximum data rate (lvds disabled); 120 ? w standby power at 3. operating temperature -40c to +105c ambient packaging 52-ball ibga, automotive-qualified; wafer or die
mt9v024_dsrev. g pub. 4/15 en 2 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description mt9v024d00xtcc13cc1-200 vga 1/3" gs cis die sales, 200 ? m thickness mt9v024d00xtmc13cc1-200 vga 1/3" gs cis die sales, 200 ? m thickness mt9v024d00xtrc13cc1-200 vga 1/3" gs cis die sales, 200 ? m thickness mt9v024d00xtrc13cc1-400 vga 1/3" gs cis die sales, 400 ? m thickness mt9v024ia7xtc-dp vga 1/3" gs cis dry pack with protective film mt9v024ia7xtc-dr vga 1/3" gs cis dry pack without protective film mt9v024ia7xtm-dp vga 1/3" gs cis dry pack with protective film mt9v024ia7xtm-dr vga 1/3" gs cis dry pack without protective film mt9v024ia7xtm-tp wvga 1/3" gs cis tape & reel with protective film mt9v024ia7xtm-tr wvga 1/3" gs cis tape & reel without protective film MT9V024IA7XTR-DP vga 1/3" gs cis dry pack with protective film mt9v024ia7xtr-dr vga 1/3" gs cis dry pack without protective film mt9v024ia7xtr-tp vga 1/3" gs cis tape & reel with protective film mt9v024ia7xtr-tr vga 1/3" gs cis tape & reel without protective film
mt9v024_dsrev. g pub. 4/15 en 2 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 color (rgb bayer) device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 serial bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 two-wire serial interface sample read and write sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 appendix a: power-on reset and standby timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 appendix b: electrical identification of cfa type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
mt9v024_dsrev. g pub. 4/15 en 3 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor list of figures list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 2: 52-ball ibga package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: typical configuration (connection) ?parallel output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 4: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: pixel color pattern detail rgb bayer (top right corner ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 6: pixel color pattern detail rccc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 7: spatial illustration of image re adout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 8: timing example of pixel data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 9: row timing and frame_valid/line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 10: timing diagram showing a write to r0x09 with the valu e 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 11: timing diagram showing a read from r0x09; returned value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 12: timing diagram showing a bytewise write to r0x09 wi th the value 0x0284 . . . . . . . . . . . . . . . . . . . .18 figure 13: timing diagram showing a bytewise read from r0x 09; returned value 0x0284 . . . . . . . . . . . . . . . .18 figure 14: simultaneous master mo de synchronization waveforms #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 15: simultaneous master mo de synchronization waveforms #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 16: sequential master mode synchron ization waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 17: snapshot mode interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 18: snapshot mode frame synchronization waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 19: exposure and readout timing (sim ultaneous mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 20: exposure and readout timing (seq uential mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 21: signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 22: latency of exposure register in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 23: sequence of control voltages at the hdr gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 24: sequence of voltages in a piecewise linear pixel resp onse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 25: 12- to 10-bit companding chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 26: latency of gain register(s) in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 27: tiled sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 28: black level calibration flow chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 29: controllable and observable aec/agc registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 30: readout of six pixels in normal and column flip ou tput mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 31: readout of six rows in normal and row flip output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 32: readout of 8 pixels in normal and row bin output mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 33: readout of 8 pixels in normal and column bin output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 34: spatial illustration of interlaced image readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 35: different line_valid formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 36: serial output format for a 6x2 frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 37: lvds timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 38: propagation delays for pixclk and data out signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 39: propagation delays for frame_vali d and line_valid signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1 figure 40: two-wire serial bus timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 41: serial host interface start condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 42: serial host interface stop condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 43: serial host interface data timing for write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 44: serial host interface data timing for read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 45: acknowledge signal timing after an 8-bit write to th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 46: acknowledge signal timing after an 8-bit read from th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 47: typical quantum efficiency?rgb bayer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 48: typical quantum efficiency?monoc hrome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 49: typical quantum efficiency?rccc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 50: 52-ball ibga. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 51: power-up, reset, cloc k, and standby sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
mt9v024_dsrev. g pub. 4/15 en 4 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 4: frame time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 5: frame time?long integration time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 6: slave address modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 7: real-time context-switchable regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 8: recommended register settings and performance impact (reserved registers) . . . . . . . . . . . . . . . .21 table 9: lvds packet format in stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 10: lvds packet format in stereoscopy mode (stereoscopy mode bit asserted) . . . . . . . . . . . . . . . . . . .46 table 11: reserved words in the pixel data stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 12: ser_dataout_* state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 13: shft_clk_* state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 14: lvds ac timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 15: dc electrical characteristics over temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 16: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 17: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 18: ac electrical characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 19: two-wire serial bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
mt9v024_dsrev. g pub. 4/15 en 5 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor general description general description the mt9v024 is a 1/3-inch wide-vga format cmos active-pixel digital image sensor with global shutter and high dynamic ran ge (hdr) operation. the sensor has specifi- cally been designed to support the demanding interior and exterior automotive imaging needs, which makes this part ideal for a wide variety of imaging applications in real- world environments. this wide-vga cmos image sensor features aptina?s breakthrough low-noise cmos imaging technology that achieves ccd image quality (based on sign al-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advan- tages of cmos. the active imaging pixel array is 752h x 480v. it incorporates sophisticated camera func- tions on-chip?such as binning 2 x 2 and 4 x 4, to improve sensitivity when operating in smaller resolutions?as well as windowing, column and row mirroring. it is program- mable through a simple two- wire serial interface. the mt9v024 can be operated in its default mode or be programmed for frame size, exposure, gain setting, and other para meters. the default mode outputs a wide-vga-size image at 60 frames per second (fps). an on-chip analog-to-digital converter (adc) pr ovides 10 bits per pi xel. a 12-bit resolu- tion companded for 10 bits for small signals ca n be alternatively enabled, allowing more accurate digitization for darker areas in the image. in addition to a traditional, parallel logic output the mt9v024 also features a serial low- voltage differential signaling (lvds) output. the sensor can be operated in a stereo- camera, and the sensor, designated as a stereo -master, is able to merge the data from itself and the stereo-slave sensor into one serial lvds stream. the sensor is designed to operate in a wide temperature range (?40c to +105c). figure 1: block diagram p ara llel vi d eo d a t a o u t se r i a l re g iste r i/o co n t r ol re g iste r adcs active-pixel se n so r (aps) a rra y 752h x 48 0v ti m i ng and co n t r ol di g it a l p r ocessi ng a na lo g p r ocessi ng se r i a l vi d eo lvds o u t sl a ve vi d eo lvds i n (fo r ste r eo app lic a tio n s o n ly)
mt9v024_dsrev. g pub. 4/15 en 6 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor general description figure 2: 52-ball ibga package a b c d e f g h 2 ser_ shft_ b ypass ser_ v dd d out 7 frame line_ 3 ser_ shft_ lvds d gnd stln_ expo- sure 1 v dd lvds b ypass ser_ d out 5 d out 6 d out 8 d out 9 4 v dd v dd s data sclk 6 d out 0 d out 1 d gnd a gnd led_ oe 7 d out 2 d out 4 a gnd nc nc v aa s_ctrl_ rsvd 5 sys- pixclk stfrm_ error to p view ( ba ll dow n ) out _valid 8 d out 3 vaapix v aa nc nc stand- reset_ s_ctrl dataout _p lvds _clkin _p gnd datain _p clkout _p datain _n valid dataout _n clkout _n gnd out lvds clk out _adr 1 adr0 b y _clkin _n b ar
mt9v024_dsrev. g pub. 4/15 en 7 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor ball descriptions ball descriptions table 1: ball descriptions 52-ball iba numbers symbol type description note h7 rsvd input connect to d gnd .1 d2 ser_datain_n input serial data in for ster eoscopy (differential negative). tie to 1k ? pull-up (to 3.3v) in non-stereoscopy mode. d1 ser_datain_p input serial data in for ster eoscopy (differential positive). tie to d gnd in non-stereoscopy mode. c2 bypass_clkin_n input input bypass shift-clk (differential negative). tie to 1k ? pull-up (to 3.3v) in non-stereoscopy mode. c1 bypass_clkin_p input input bypass shift-clk (differential positive). tie to d gnd in non- stereoscopy mode. h3 exposure input rising edge starts exposure in snapshot and slave modes. h4 sclk input two-wire serial interface clock. connect to v dd with 1.5k resistor even when no other two-wire serial interface peripheral is attached. h6 oe input d out enable pad, active high. 2 g7 s_ctrl_adr0 input two-wire serial interface slave address select (see table 4 on page 12). h8 s_ctrl_adr1 input two-wire serial interface slave address select (see table 4 on page 12). g8 reset_bar input asynchronous reset. all registers assume defaults. f8 standby input shut down sensor operation for power saving. a5 sysclk input master clock (26.6 mhz; 13 mhz C 27 mhz). g4 s data i/o two-wire serial interface data. connect to v dd with 1.5k resistor even when no other two-wire serial interface peripheral is attached. g3 stln_out i/o output in master mode ? start line sync to drive slave chip in- phase; input in slave mode. g5 stfrm_out i/o output in master mode ? start frame sync to drive a slave chip in- phase; input in slave mode. h2 line_valid output asserted when d out data is valid. g2 frame_valid output asserted when d out data is valid. e1 d out 5 output parallel pixel data output 5. f1 d out 6 output parallel pixel data output 6. f2 d out 7 output parallel pixel data output 7. g1 d out 8 output parallel pixel data output 8 h1 d out 9 output parallel pixel data output 9. h5 error output error detected. directly connected to stereo error flag. g6 led_out output led strobe output. b7 d out 4 output parallel pixel data output 4. a8 d out 3 output parallel pixel data output 3. a7 d out 2 output parallel pixel data output 2. b6 d out 1 output parallel pixel data output 1. a6 d out 0 output parallel pixel data output 0. b5 pixclk output pixel clock out. d out is valid on rising edge of this clock.
mt9v024_dsrev. g pub. 4/15 en 8 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor ball descriptions notes: 1. pin h7 (rsvd) must be tied to gnd. 2. output enable (oe) tri-states signals d out 0Cd out 9, line_valid, frame_valid, and pixclk. 3. no connect. these pins must be left floating for proper operation. figure 3: typical configuration (connection) ? parallel output mode note: lvds signals are to be left floating. b3 shft_clkout_n output output shift clk (differential negative). b2 shft_clkout_p output output shift clk (differential positive). a3 ser_dataout_n output serial data out (differential negative). a2 ser_dataout_p output serial data out (differential positive). b4, e2 v dd supply digital power 3.3v. c8, f7 v aa supply analog power 3.3v. b8 vaapix supply pixel power 3.3v. a1, a4 v dd lvds supply dedicated power for lvds pads. b1, c3 lvdsgnd ground dedicated gnd for lvds pads. c6, f3 d gnd ground digital gnd. c7, f6 a gnd ground analog gnd. e7, e8, d7, d8 nc nc no connect. 3 table 1: ball descriptions (continued) 52-ball iba numbers symbol type description note sysclk line_valid frame_valid pixclk d out (9:0) stand b y exposure rsvd s_ctrl_adr0 s_ctrl_adr 1 lvdsgnd led_out error s data sclk reset_ b ar oe v dd lvds a gnd d gnd v dd v aa vaapix m a ste r clock 0. 1 f to co n t r olle r stand b y f r o m co n t r olle r o r di g it a l gnd two-wi r e se r i a l i n te r f a ce v dd v aa vaapix to led o u t pu t 1 0k 1 .5k
mt9v024_dsrev. g pub. 4/15 en 9 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor pixel data format pixel data format pixel array structure the mt9v024 pixel array is configured as 809 columns by 499 rows, shown in figure 4. the dark pixels are optically black and are used internally to monitor black level. of the left 52 columns, 36 are dark pixels used for row noise correction. of the top 14 rows of pixels, two of the dark rows are used for black level correction. also, three black rows from the top black rows can be read out by setting the show dark rows bit in the read mode register; setting show dark columns will display the 36 dark columns. there are 753 columns by 481 rows of optically active pi xels. while the sensor's format is 752 x 480, one additional active column and active ro w are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. this one pixel adjustment is always performed, for monochrome or color versions. the active area is surrounded with optically transparent dummy pixels to improve image unifor- mity within the active area. neither dummy pi xels nor barrier pixels can be read out. figure 4: pixel array description (0, 0) 3 b arr ie r + 38 ( 1 + 3 6 addr esse d + 1 ) dar k + 9 b arr ie r + 2 li g ht dumm y 2 b arr ie r + 2 li g ht dumm y 2 b arr ie r + 2 li g ht dumm y a ctive p ixel li g ht dumm y p ixel dar k p ixel b arr ie r p ixel 4 .92 x 3 .05 mm 2 pixel a rra y 8 09 x 4 99 (75 3 x 481 a ctive) 6.0 m p ixel 2 b arr ie r + 8 (2 + 4 addr esse d + 2) dar k + 2 b arr ie r + 2 li g ht dumm y
mt9v024_dsrev. g pub. 4/15 en 10 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor pixel data format figure 5: pixel color pattern detail rgb bayer (top right corner) figure 6: pixel color pattern detail rccc active pixel (0,0) a rra y pixel ( 4 , 14 ) row re ad o u t di r ectio n b g b g b g g r g r g r g r g r g r g r g r g r g r g r g r b g b g b g b g b g b g b g b g b g col umn re ad o u t di r ectio n active pixel (0, 0) array pixel (4, 14) . . . . . . ... c c c c c c c c c c c c c c c c c c c c c c c c r c r c r c r c r c r c r c r cc r column readout direction row readout direction
mt9v024_dsrev. g pub. 4/15 en 11 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor color (rgb bayer) device limitations color (rgb bayer) device limitations the color version of the mt9v024 does not support or offers reduced performance for the following functionalities. pixel binning pixel binning is done on immedi ate neighbor pixels only, no facility is provided to skip pixels according to a bayer pattern. therefore, the result of binning combines pixels of different colors. see ?pixel binning? on page 36 for additional information. interlaced readout interlaced readout yields one field consisting only of red and green pixels and another consisting only of blue and green pixels. this is due to the bayer pattern of the cfa. automatic black level calibration when the color bit is set (r0x0f[1]=1), the sensor uses black level correction values from one green plane, which are applied to all colors. to use the calibration value based on all dark pixels' offset values, the color bit should be cleared. defective pixel correction for defective pixel correction to calculate replacement pixel values correctly, for color sensors the color bit must be set (r0x0f[1] = 1). however, the color bit also applies unequal offset to the color planes, and the results might not be acceptable for some applications. other limiting factors black level correction and row-wise noise correction are applied uniformly to each color. the row-wise noise correction algorithm does not work well in color sensors. automatic exposure and gain control calculations are ma de based on all three colors, not just the green channel. high dynamic range does operate in color; however, aptina strongly recommends limiting use to linear operation where good color fidelity is required.
mt9v024_dsrev. g pub. 4/15 en 12 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor output data format output data format the mt9v024 image data can be read out in a progressive scan or interlaced scan mode. valid image data is surrounded by horizontal and vertical blanking, as shown in figure 7. the amount of horizontal and vertical bl anking is programmable through r0x05 and r0x06, respectively (r0xcd and r0xce for co ntext b). lv is high during the shaded region of the figure. see ?output data ti ming? on page 9 for the description of fv timing. figure 7: spatial illustration of image readout p 0,0 p 0, 1 p 0,2 .....................................p 0, n - 1 p 0, n p 1 ,0 p 1 , 1 p 1 ,2 .....................................p 1 , n - 1 p 1 , n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m - 1 ,0 p m - 1 , 1 .....................................p m - 1 , n - 1 p m - 1 , n p m ,0 p m , 1 .....................................p m , n - 1 p m , n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal b lanking vertical b lanking vertical/horizontal b lanking
mt9v024_dsrev. g pub. 4/15 en 13 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor output data format output data timing the data output of the mt9v024 is sync hronized with the pixclk output. when line_valid (lv) is high, one 10-bit pixe l datum is output every pixclk period. figure 8: timing example of pixel data the pixclk is a nominally inverted version of the master clock (sysclk). this allows pixclk to be used as a clock to latch the data. however, when column bin 2 is enabled, the pixclk is high for one complete master clock master period and then low for one complete master clock period; when column bin 4 is enabled, the pixclk is high for two complete master clock periods and then low for two complete master clock periods. it is continuously enabled, even during the blanking period. setting r0x72 bit[4] = 1 causes the mt9v024 to invert the polarity of the pixclk. the parameters p1, a, q, and p2 in figure 9 are defined in table 2. figure 9: row timing and frame_valid/line_valid signals table 2: frame time parameter name equation default timing at 26.66 mhz aactive data time context a: r0x04 context b: r0xcc 752 pixel clocks = 752 master = 28.20 ? s p1 frame start blanking context a: r0x05 - 23 context b: r0xcd - 23 71 pixel clocks = 71master = 2.66 ? s p2 frame end blanking 23 (fixed) 23 pixel clocks = 23 master = 0.86 ? s q horizontal blanking context a: r0x05 context b: r0xcd 94 pixel clocks = 94 master = 3.52 ? s line_valid pixclk d out (9:0) p 0 (9:0) p 1 (9:0) p2 (9:0) p 3 (9:0) p 4 (9:0) p n - 1 (9:0) p n (9:0) v a li d i mag e d a t a b l an ki ng b l an ki ng ... ... ... ... p 1 a q a q a p2 n um be r of ma ste r clocks frame_valid line_valid ... ... ...
mt9v024_dsrev. g pub. 4/15 en 14 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor output data format sensor timing is shown above in terms of pi xel clock and master clock cycles (refer to figure 8 on page 9). the recommended master clock frequency is 26.66 mhz. the vertical blanking and the total frame time equations assume that the integration time (coarse shutter width plus fine shutter width) is less than the number of active rows plus the blanking rows minus the overhead rows: window height + vertical blanking ? 2 (eq 1) if this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in table 3. in this example, it is assumed that the coarse shutter width control is programmed with 523 rows and the fine shutter width total is zero. for simultaneous mode, if the exposure time registers (coarse shu tter width total plus fine shutter width total) exceed the total re adout time, then the vertical blanking time is internally extended auto matically to adjust for the additional integration time required. this extended value is not written back to the vertical blanking registers. the vertical blank register can be used to adjust frame-to-frame readout time. this register does not affect the exposure time but it may extend the readout time. note: the mt9v024 uses column parallel analog-digital converters; thus short row timing is not possi- ble. the minimum total row time is 704 columns (horizontal width + horizontal blanking). the minimum horizontal blanking is 61 for normal mode, 71 for column bin 2 mode, and 91 for col- umn bin 4 mode. when the window width is se t below 643, horizontal blanking must be increased. in binning mode, the minimum row time is r0x04+r0x05 = 704. a+q row time context a: r0x04 + r0x05 context b: r0xcc + r0xcd 846 pixel clocks = 846 master = 31.72 ? s v vertical blanking context a: (r0x06) x (a + q) + 4 context b: (r0xce) x (a + q) + 4 38,074 pixel clocks = 38,074 master = 1.43ms nrows x (a + q) frame valid time context a: (r0x03) (a + q) context b: (r0xcb) x (a + q) 406,080 pixel clocks = 406,080 master = 15.23ms f total frame time v + (nrows x (a + q)) 444,154 pixel clocks = 444,154 master = 16.66ms table 3: frame timelong integration time parameter name equation (number of master clock cycles) default timing at 26.66 mhz v vertical blanking (long integration time) context a: (r0x0b + 2 - r0x03) (a + q) + r0xd5 + 4 context b: (r0xd2 + 2 - r0xcb) x (a + q) + r0xd8 + 4 38,074 pixel clocks = 38,074 master = 1.43ms f total frame time (long integration time) context a: (r0x0b + 2) (a + q) + r0xd5 + 4 context b: (r0xd2 + 2) x (a + q) + r0xd8 + 4 444,154 pixel clocks = 444,154 master = 16.66ms table 2: frame time (continued) parameter name equation default timing at 26.66 mhz
mt9v024_dsrev. g pub. 4/15 en 15 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor serial bus description serial bus description registers are written to and read from the mt9v024 through the two-wire serial inter- face bus. the mt9v024 is a serial interface sl ave with four possible ids (0x90, 0x98, 0xb0 and 0xb8) determined by the s_ctrl_adr0 and s_ctrl_adr1 input pins. data is transferred into the mt9v024 and out through the serial data (s data ) line. the s data line is pulled up to v dd off-chip by a 1.5k ? resistor. either the slave or master device can pull the s data line down?the serial interface pr otocol determines which device is allowed to pull the s data line down at any given time. the registers are 16-bit wide, and can be accessed through 16- or 8-bit two-wire serial interface sequences. protocol the two-wire serial interface defines several different transmission codes, as shown in the following sequence: 1. a start bit 2. the slave device 8-bit address 3. a(n) (no) acknowledge bit 4. an 8-bit message 5. a stop bit start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high. slave address the 8-bit address of a two-wire serial interfac e device consists of 7 bits of address and 1 bit of direction. a ?0? in the lsb of the address indicates write mode, and a ?1? indi- cates read mode. as indicated above, the mt 9v024 allows four poss ible slave addresses determined by the two input pi ns, s_ctrl_adr0 and s_ctrl_adr1. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) re leases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence. stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high.
mt9v024_dsrev. g pub. 4/15 en 16 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor serial bus description sequence a typical read or write sequence begins by the master sending a start bit. after the start bit, the master sends the slave device?s 8-bit address. the last bit of the address determines if the request is a read or a wr ite, where a ?0? indicates a write and a ?1? indicates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the 8-bit register address to which a write should take place. the slave sends an acknowledge bit to indicate that the register address has been received. the master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. the mt9v024 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are transferred, the register ad dress is automatically incremented, so that the next 16 bits are written to the next regi ster address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as foll ows. first the master sends the write mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read mode slave addres s. the master then clocks out the register data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is automatically incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. the mt9v024 allows for 8-bit data transfers through the two-wire serial interface by writing (or reading) the most significant 8 bits to the register and then writing (or reading) the least significant 8 bits to byte-wise address register (0x0f0). bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits. data bit transfer one data bit is transferred during each clock pulse. the two-wire serial interface clock pulse is provided by the master. the data must be stable during the high period of the serial clock?it can only change when the two-wire serial interface clock is low. data is transferred 8 bits at a time, fo llowed by an acknowledge bit. table 4: slave address modes {s_ctrl_adr1, s_ctrl_adr0} slave address write/read mode 00 0x90 write 0x91 read 01 0x98 write 0x99 read 10 0xb0 write 0xb1 read 11 0xb8 write 0xb9 read
mt9v024_dsrev. g pub. 4/15 en 17 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor two-wire serial interface sample read and write sequences two-wire serial interface sample read and write sequences 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 10. a start bit given by the master, followed by the write address, starts the sequence. the image sensor then gives an acknowledge bit and expects the re gister address to come first, followed by the 16-bit data. after each 8-bit the image sensor gives an acknowledge bit. all 16 bits must be written before the register is update d. after 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register. the master stops writing by sending a start or stop bit. figure 10: timing diagram showing a write to r0x09 with the value 0x0284 16-bit read sequence a typical read sequence is shown in figure 11. first the master has to write the register address, as in a write sequence. then a start bit and the read address specifies that a read is about to happen from the register. the master then clocks out the register data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is auto-incremented af ter every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 11: timing diagram showing a re ad from r0x09; returned value 0x0284 sclk s data start ack 0x b8 addr ack ack ack stop r0x09 1 000 0 1 00 0000 00 1 0 sclk s data start ack 0x b8 addr 0x b 9 addr 0000 00 1 0 r0x09 ack ack ack stop 1 000 0 1 00 nack
mt9v024_dsrev. g pub. 4/15 en 18 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor two-wire serial interface sample read and write sequences 8-bit write sequence to be able to write 1 byte at a time to the re gister a special register address is added. the 8-bit write is done by first writing the upper 8 bits to the desired register and then writing the lower 8 bits to the bytewise address regist er (r0xf0). the register is not updated until all 16 bits have been written. it is not po ssible to just update half of a register. in figure 12, a typical sequence for 8-bit writing is shown. the second byte is written to the bytewise register (r0xf0). figure 12: timing diagram showing a bytewise write to r0x09 with the value 0x0284 8-bit read sequence to read one byte at a time the same special register address is used for the lower byte. the upper 8 bits are read from the desired register. by following this with a read from the byte-wise address register (r0xf0) the lower 8 bits are accessed (figure 13). the master sets the no-acknowledge bits shown. figure 13: timing diagram showing a bytewis e read from r0x09; returned value 0x0284 stop r0xf0 ack start 0x b8 addr ack s data sclk ack ack ack ack r0x09 0x b8 addr 0000 00 1 0 1 000 0 1 00 start start 0x b 9 addr s data sclk stop nack ack ack ack r0x09 start 0x b8 addr 0000 00 1 0 start 0x b 9 addr s data sclk nack ack ack ack r0xf0 start 0x b8 addr 1 000 0 1 00
mt9v024_dsrev. g pub. 4/15 en 19 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor two-wire serial interface sample read and write sequences register lock included in the mt9v024 is a register lock (r0xfe) feature that can be used as a solution to reduce the probability of an inadverten t noise-triggered two-wire serial interface write to the sensor. all registers, or only the read mode registers?r0x0d and r0x0e, can be locked. it is important to prevent an inad vertent two-wire serial interface write to the read mode registers in automotive applicatio ns since this register controls the image orientation and any unintended flip to an image can cause serious results. at power-up, the register lock defaults to a value of 0xbeef, which implies that all registers are unlocked and any two-wire seri al interface writes to the register gets committed. lock all registers if a unique pattern (0xdead) to r0xfe is programmed, any subseque nt two-wire serial interface writes to registers (except r0xfe) are not committed. alternatively, if the user writes a 0xbeef to the register lock re gister, all registers are unlocked and any subsequent two-wire serial interface writes to the register are committed. lock only read mode registers (r0x0d and r0x0e) if a unique pattern (0xdeaf) to r0xfe is programmed, any subsequent two-wire serial interface writes to r0x0d or r0x0e are not comm itted. alternatively, if the user writes a 0xbeef to register lock register, regist ers r0x0d and r0x0e are unlocked and any subsequent two-wire serial interface writes to these registers are committed.
mt9v024_dsrev. g pub. 4/15 en 20 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor two-wire serial interface sample read and write sequences real-time context switching in the mt9v024, the user may switch between tw o full register sets (listed in table 5) by writing to a context switch change bit in regist er 0x07. this context switch will change all registers (no shadowing) at the frame start time and have the new values apply to the immediate next exposure and readout time (frame n+1), except for shutter width and v1-v4 control, which will take effect for next exposure but will show up in the n+2 image. . table 5: real-time context-switchable registers register name register number (hex) for context a register number (hex) for context b column start 0x01 0xc9 row start 0x02 0xca window height 0x03 0xcb window width 0x04 0xcc horizontal blanking 0x05 0xcd vertical blanking 0x06 0xce coarse shutter width 1 0x08 0xcf coarse shutter width 2 0x09 0xd0 coarse shutter width control 0x0a 0xd1 coarse shutter width total 0x0b 0xd2 fine shutter width 1 0xd3 0xd6 fine shutter width 2 0xd4 0xd7 fine shutter width total 0xd5 0xd8 read mode 0x0d [5:0] 0x0e [5:0] high dynamic range enable 0x0f [0] 0x0f [8] adc resolution control 0x1c [1:0] 0x1c [9:8] v1 control C v4 control 0x31 C 0x34 0x39 C 0x3c analog gain control 0x35 0x36 row noise correction control 1 0x70 [1:0] 0x70 [9:8] tiled digital gain 0x80 [3:0] C 0x98 [3:0] 0x80 [11:8] C 0x98 [11:8] aec/agc enable 0xaf [1:0] 0xaf [9:8]
mt9v024_dsrev. g pub. 4/15 en 21 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor two-wire serial interface sample read and write sequences recommended register settings table 6 describes new suggested register settings, and descriptions of performance improvements and conditions: table 6: recommended register settings and performance impact (reserved registers) register current default new setting performance impact r0x20 0x01c1 0x03c7 recommended by design to improve performance in hdr mode and when frame rate is low. we also recommended using r0x13=0x2d2e with this setting for better column fpn. note: when coarse integration time set to 0 and fine integration time less than 456, r0x20 should be set to 0x01c7 r0x24 0x0010 0x001b corrects pixel negative dark offset when global reset in r0x20[9] is enabled. r0x2b 0x0004 0x0003 improves column fpn. r0x2f 0x0004 0x0003 improves fpn at near-saturation.
mt9v024_dsrev. g pub. 4/15 en 22 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description feature description operational modes the mt9v024 works in master, snapshot, or slave mode. in master mode the sensor generates the readout timing. in snapshot mode it accepts an external trigger to start integration, then generates the readout timi ng. in slave mode the sensor accepts both external integration and readout controls. th e integration time is programmed through the two-wire serial interface during master or snapshot modes, or controlled through an externally generated control signal during slave mode. master mode there are two possible operation methods fo r master mode: simultaneous and sequen- tial. one of these operation modes must be selected through the two-wire serial inter- face. additional details on this mode can be found in tn-09-224 master exposure mode operation. simultaneous master mode in simultaneous master mode, the exposure period occurs during readout. the frame synchronization waveforms are shown in figure 14 and figure 15. the exposure and readout happen in parallel rather than sequen tial, making this the fastest mode of oper- ation. figure 14: simultaneous master mode synchronization waveforms #1 exposure time frame time t led2fv-sim led_out frame_valid line_valid t led2fv-sim t vblank
mt9v024_dsrev. g pub. 4/15 en 23 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description figure 15: simultaneous master mode synchronization waveforms #2 when exposure time is greater than the su m of vertical blank and window height, the number of vertical blank rows is increase d automatically to accommodate the exposure time. sequential master mode in sequential master mode the exposure period is followed by readout. the frame synchronization waveforms for sequential master mode are shown in figure 16. the frame rate changes as the integration time changes. figure 16: sequential master mode synchronization waveforms snapshot mode in snapshot mode the sensor accepts an input trigger signal which initiates exposure, and is immediately followed by readout. figure 17 shows the interface signals used in snapshot mode. in snapshot mode, the start of the integration period is determined by the externally applied exposure pulse that is input to the mt9v024. the integration time is preprogrammed at r0x0b or r0xd2 th rough the two-wire serial interface. after the frame's integration period is complete the readout process commences and the syncs and data are output. sensor in snapshot mode can capture a single image or a sequence of images. the frame rate may only be controlled by changing the period of exposure time frame time t led2fv-sim t vblank t ledoff led_out frame_valid line_valid exposure time frame time led_out frame_valid line_valid t vblank t led2fv-seq t fv2led-seq
mt9v024_dsrev. g pub. 4/15 en 24 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description the user supplied exposure pulse train. the frame synchronization waveforms for snapshot mode are shown in figure 18 on page 20. additional details on this mode can be found in tn-09-225 snapshot exposure mode operation. figure 17: snapshot mode interface signals figure 18: snapshot mode fr ame synchronization waveforms slave mode in slave mode, the exposure and readout are controlled using the exposure, stfrm_out, and stln_out pins. when the slave mode is enabled, stfrm_out and stln_out become input pins. the start and end of integration are contro lled by exposure and stfrm_out pulses, respectively. while a stfrm_out pulse is used to stop integration, it is also used to enable the readout process. after integration is stopped, the user provid es stln_out pulses to trigger row readout. a full row of data is read out with each stln_out pulse. the user must provide enough time between successive stln_o ut pulses to allow the comp lete readout of one row. it is also important to provide additional st ln_out pulses to allow the sensors to read the vertical blanking rows. it is recommended that the user program the vertical blank register (r0x06) with a value of 4, and ac hieve additional vertic al blanking between frames by delaying the application of the stfrm_out pulse. controller exposure sysclk pixclk line_valid frame_valid d out (9:0) mt9v02 4 exposure time frame time t ew t e2e t led2fv t fv2e t vblank t e2led exposure led_out frame_valid line_valid
mt9v024_dsrev. g pub. 4/15 en 25 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description the elapsed time between the rising edge of stln_out and the first valid pixel data is calculated for context a by [horizontal blanking register (r0x05) + 4] clock cycles. for context b, the time is (r0xcd + 4) clock cycles. additional details on this mode can be found in tn-09-283 slave exposure mode opera- tion. figure 19: exposure and readout timing (simultaneous mode) notes: 1. not drawn to scale. 2. frame readout shortened for clarity. 3. simultaneous progressive scan readout mode shown. exposure stfrm_out stln_out frame_valid line_valid led_out exposure time t ew t s f2sf t sf2fv t e2sf t e2led t sf2led t fv2sf t sfw
mt9v024_dsrev. g pub. 4/15 en 26 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description figure 20: exposure and readout timing (sequential mode) notes: 1. not drawn to scale. 2. frame readout shortened for clarity. 3. stln_out pulses are optional during exposure time. 4. sequential progressive scan readout mode shown. signal path the mt9v024 signal path consists of a programmable gain, a pr ogrammable analog offset, and a 10-bit adc. see ?black leve l calibration? on page 32 for the programmable offset operation description. figure 21: signal path t ew exposure time t e2sf t sf2sf t sf2fv t fv2e t sfw t sf2led t e2led exposure stfrm_out stln_out frame_valid line_valid led_out pixel o u t pu t ( r eset m i nu s si gna l) offset co rr ectio n volt ag e (r0x 48 o r r es u lt of b lc) 1 0 ( 1 2) bit adc adc d a t a (9:0) g a i n selectio n (r0x 3 5 o r r0x 3 6 o r r es u lt of agc) v ref (r0x2c) c2 c 1
mt9v024_dsrev. g pub. 4/15 en 27 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description on-chip biases adc voltage reference the adc voltage reference is programmed th rough r0x2c, bits 2:0. the adc reference ranges from 1.0v to 2.1v. the default value is 1.4v. the increment size of the voltage reference is 0.1v from 1.0v to 1.6v (r0x2c[2:0] values 0 to 6). at r0x2c[2:0] = 7, the refer- ence voltage jumps to 2.1v. it is very important to preserve the correct va lues of the other bits in r0x2c. the default register setting is 0x0004. this corresponds to 1.4v?at this setting 1mv input to the adc equals approximately 1 lsb. v_step voltage reference this voltage is used for pixel high dynamic range operations, programmable from r0x31 through r0x34 for context a, or r0x39 through r0x3b for context b. chip version chip version register r0x00 is read-only. window control registers column start a/b, row start a/b, window height a/b (row size), and window width (column size ) a/b control the size and starting coordinates of the window. the values programmed in the window height and width registers are the exact window height and width out of the sensor. the wind ow start value should never be set below four. to read out the dark rows set bit 6 of r0x0d. in addition, bit 7 of r0x0d can be used to display the dark columns in the image. note that there are show dark settings only for context a. blanking control horizontal blank and vertical blank registers r0x05 and r0x06 (b: 0xcd and r0xce), respectively, control the blan king time in a row (horizontal blanking) and between frames (vertical blanking). ? horizontal blanking is specified in terms of pixel clocks. ? vertical blanking is specified in terms of numbers of rows. the actual imager timing can be calculat ed using table 2 on page 9 and table 3 on page 10, which describe ?row timing and fv/lv signals.? the minimum number of vertical blank rows is 4.
mt9v024_dsrev. g pub. 4/15 en 28 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description pixel integration control total integration total integration time is the result of coar se shutter width and fine shutter width regis- ters, and depends also on whether manual or automatic exposure is selected. the actual total integration time, t int is defined as: t int = t intcoarse + t intfint (eq 2) = (number of rows of integration x row time) + (number of pixels of integration x pixel time) where: ? number of rows of integration (auto exposure control: enabled) when automatic exposure control (aec) is enabled, the number of rows of integra- tion may vary from frame to frame, with the limits controlled by r0xac (minimum coarse shutter width) and r0xad (maximum coarse shutter width). ? number of rows of integration (auto exposure control: disabled) if aec is disabled, the number of rows of integration equals the value in r0x0b. or if context b is enabled, the number of rows of integration equals the value in r0xd2. ? number of pixels of integration the number of fine shutter width pixels is independent of aec mode (enabled or disabled): ? context a: the number of pixels of integration equals the value in r0xd5. ? context b: the number of pixels of integration equals the value in r0xd8. row timing context a: row time = (r0x04 + r0x05) master clock periods (eq 3) context b: row time = (r0xcc + r0xcd) master clock periods (eq 4) typically, the value of the coarse shutter wi dth total registers is limited to the number of rows per frame (which includ es vertical blanking rows), such that the frame rate is not affected by the integration time. if the coar se shutter width total is increased beyond the total number of rows per frame, the user must add additional blanking rows using the vertical blanking registers as needed. see descriptions of the vertical blanking regis- ters, r0x06 and r0xce in table 1and table 2 of the mt9v024 register reference. a second constraint is that t int must be adjusted to avoi d banding in the image from light flicker. under 60hz flicke r, this means the frame time mu st be a multiple of 1/120 of a second. under 50hz flicker, the frame time must be a multiple of 1/100 of a second.
mt9v024_dsrev. g pub. 4/15 en 29 ?semiconductor components industries, llc, 2015 mt9v024: 1/3-inch wide-vga digital image sensor feature description changes to integration time with automatic exposure control disabled (r0xaf[0] for cont ext a, or r0xaf[8] for context b) and if the total inte- gration time (r0x0b or r0xd2) is changed through the two-wire serial interface while fv is asserted for frame n , the first frame output using the ne w integration time is frame ( n + 2 ). similarly, when automatic exposure control is enabled, any change to the integration time for frame n first appears in frame ( n + 2 ) output. additional details on this latency can be found in tn-09-226 latency of exposure or gain switch. the sequence is as follows: 1. during frame n , the new integration time is held in the r0x0b or r0d2 live register. 2. prior to the start of frame ( n + 1 ) readout, the new integration time is transferred to the exposure control module. integration for each row of frame ( n + 1 ) has been completed using the old integration time. the earliest time that a row can start integrating using the new integration time is immediately after th at row has been read for frame ( n + 1 ). the actual time that rows start integrating usin g the new integration time is dependent on the new value of the integration time. 3. when frame ( n + 2 ) is read out, it is integrated using the new in tegration time. if the integration time is changed (r0x0b or r0xd2 written) on successive frames, each va lue written is applied to a single frame; the latency between writing a value and it affecting the frame readout remains at two frames. figure 22: latency of exposure register in master mode idle idle write new exposure value (exp b) exp a exp a frame-start readout exp a readout exp a readout exp b readout exp b readout exp b two-wire serial interface (input) led_out (output) frame_valid (output) aec-sample writes new exposure value (exp b) aec-sample point exp b exp b exp b frame n frame n+1 frame n+2 new image available at output frame-start activates new exposure value (exp b)
mt9v024_dsrev. g pub. 4/15 en 30 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description exposure indicator the exposure indicator is controlled by: ?r0x1b led_out control the mt9v024 provides an output pin, led_out, to indicate when the exposure takes place. when r0x1b bit 0 is clear, led_out is high during exposure. by using r0x1b, bit 1, the polarity of the led_out pin can be inverted. high dynamic range high dynamic range is controlled by: in the mt9v024, high dynamic range (by setting r0x0f, bit 0 or 8 to 1) is achieved by controlling the saturation level of the pixel (hdr or high dynamic range gate) during the exposure period. the sequence of the contro l voltages at the hdr gate is shown in figure 23. after the pixels are reset, the step voltage, v_step, which is applied to hdr gate, is set up at v1 for integration time t 1, then to v2 for time t 2 , then v3 for time t 3 , and finally it is parked at v4, which also serves as an antiblooming voltage for the photode- tector. this sequence of voltages leads to a piecewise linear pixel response, illustrated (approximately) in figure 23 and in figure 24 on page 27. figure 23: sequence of control voltages at the hdr gate context a context b high dynamic enable r0x0f[0] r0x0f[8] shutter width 1 r0x08 r0xcf shutter width 2 r0x09 r0xd0 shutter width control r0x0a r0xd1 v_step voltages r0x31-r0x34 r0x39-r0x3c t 2 t 3 v 4 ~0. 8 v ex p os ur e t 1 hdr volt ag e v aa ( 3 . 3 v) v 1 ~ 1 . 4 v v2~ 1 .2v v 3 ~ 1 .0v
mt9v024_dsrev. g pub. 4/15 en 31 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description figure 24: sequence of voltages in a piecewise linear pixel response the parameters of the step voltage v_step, which take values v1, v2, and v3, directly affect the position of the knee points in figure 24. light intensities work approximately as a reci procal of the partial exposure time. typi- cally, t 1 is the longest exposure, t 2 shorter, and so on. thus the range of light intensities is shortest for the first slope, providing the highest sensitivity. the register settings for v_step and partial exposures are: v1 = r0x31, bits 5:0 (context b: r0x39, bits 5:0) v2 = r0x32, bits 5:0 (context b: r0x3a, bits 5:0) v3 = r0x33, bits 5:0 (context b: r0x3b, bits 5:0) v4 = r0x34, bits 5:0 (context b: r0x3c, bits 5:0) t int = t 1 + t 2 + t 3 there are two ways to specify the knee points timing, the first by manual setting and the second by automatic knee point adjustment. knee point auto adjust is controlled for context a by r0x0a[8] (where default is on ), and for context b by r0xd1[8] (where default is off ). when the knee point auto adjust enabler is enabled (set high), the mt9v024 calculates the knee points automatically using the following equations: t 1 = t int ? t 2 ? t 3 (eq 5) t 2 = t int x (?) r0x0a[3:0] or r0xd1[3:0] (eq 6) t 3 = t int x (?) r0x0a[7:4] or r0xd1[7:4] (eq 7) as a default for auto exposure, t 2 is 1/16 of t int , t 3 is 1/64 of t int . when the auto adjust enabler is disabled (set low), t 1 , t 2 , and t 3 may be programmed through the two-wire serial interface: t 1 = coarse sw1 (row-times) + fine sw1 (pixel-times) (eq 8) t 2 = coarse sw2 ? coarse sw 1 + fine sw2 - fine sw1 (eq 9) t 3 = total integration ? t 1 ? t 2 (eq 10) = coarse total shutter width + fine shutter width total ? t 1 ? t 2 d v 1 d v2 d v 3 1 /t 1 1 /t 2 1 /t 3 li g ht i n te n sity o u t pu t
mt9v024_dsrev. g pub. 4/15 en 32 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description for context a these become: t 1 = r0x08 + r0xd3 (eq 11) t 2 = r0x09 - r0x08 + r0xd4 ? r0xd3 (eq 12) t 3 = r0x0b + r0xd4 ? t 1 ? t 2 (eq 13) for context b these are: t 1 = r0xcf + r0xd6 (eq 14) t 2 = r0xd0 - r0xcf + r0xd7 - r0xd6 (eq 15) t 3 = r0xd2 + r0xd8 -t 1 -t 2 (eq 16) in all cases above, the coarse component of total integration time may be based on the result of aec or values in r0x0b and r0xd2, depending on the settings. similar to fine shutter width total registers, the user must not set the fine shutter width 1 or fine shutter width 2 register to exceed the row time (horizontal blanking + window width). the absolute maximum value for the fine shutter width registers is 1774 master clocks. adc companding mode by default, adc resolution of the sensor is 10-bit. addition ally, a companding scheme of 12-bit into 10-bit is enabled by the adc co mpanding mode register. this mode allows higher adc resolution, which means less quantization noise at low light, and lower reso- lution at high light, where good adc quantiza tion is not so critical because of the high level of the photon?s shot noise. figure 25: 12- to 10-bit companding chart 256 512 768 1,024 4,096 2,048 1,024 512 256 4 to 1 companding (512 - 2047 384 - 767) 8 to 1 companding (2,048- 4095 768- 1023) 10-bit codes 12-bit codes 2 to 1 companding (256- 511 256- 383) no companding (0 -255 0 -255)
mt9v024_dsrev. g pub. 4/15 en 33 ?semiconductor components industries, llc, 2015 mt9v024: 1/3-inch wide-vga digital image sensor feature description gain settings changes to gain settings when the analog gain (r0x35 for context a or r0x36 for context b) or the digital gain settings (r0x80 ? r0x98) are changed, the gain is updated on the next frame start. the gain setting must be written before the frame boundary to take effect the next frame. the frame boundary is slightly after the falling edge of frame_valid. in figure 26 this is shown by the dashed vertical line labeled frame start. both analog and digital gain change regardless of whethe r the integration time is also changed simultaneously. digital gain will change as soon as the register is written. additional details on this latency can be found in tn-09- 226 latency of exposure or gain switch. figure 26: latency of gain register(s) in master mode idle idle write new gain value (gain b) frame-start readout gain a readout gain b readout gain b readout gain b readout gain b two-wire serial interface (input) led_out (output) frame_valid (output) frame-start writes new gain value (gain b) agc-sample point readout gain a agc-sample activates new gain value (gain b) frame n frame n+1 frame n+2 new image available at output
mt9v024_dsrev. g pub. 4/15 en 34 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description analog gain analog gain is controlled by: ? r0x35 global gain context a ? r0x36 global gain context b the formula for gain setting is: gain = bits[6:0] x 0.0625 (eq 17) the analog gain range supported in the mt9v024 is 1x ? 4x with a step size of 6.25 percent. to control gain manually with this register, the sensor must not be in agc mode. when adjusting the luminosity of an im age, it is recommended to alter exposure first and yield to gain increases only when the exposure value has reached a maximum limit. analog gain = bits (6:0) x 0.0625 for values 16?31 analog gain = bits (6:0)/2 x 0.125 for values 32?64 for values 16?31: each lsb increases analog gain 0.0625v/v. a value of 16 = 1x gain. range: 1x to 1.9375x. for values 32?64: each 2 lsb increases analog gain 0.125v/v (that is, double the gain increase for 2 lsb). range: 2x to 4x. odd values do not result in gain increases; the gain increases by 0.125 for values 32, 34, 36, and so on. digital gain digital gain is controlled by: ? r0x99-r0xa4 tile coordinates ? r0x80-r0x98 tiled digital gain and weight in the mt9v024, the gain logic divides the image into 25 tiles, as shown in figure 27 on page 31. the size and gain of each tile can be adjusted using the above digital gain control registers. separate tile gains can be assigned for context a and context b. registers 0x99?0x9e and 0x9f?0xa4 represen t the coordinates x0/5?x5/5 and y0/5?y5/5 in figure 27 on page 31, respectively. digital gains of registers 0x80?0x98 apply to their corresponding tiles. the mt9v024 supports a digital gain of 0.25?3.75x. when binning is enabled, the tile offsets maintain their absolute values; that is, tile coor- dinates do not scale with row or column bin se tting. digital gain is applied as soon as register is written. note: there is one exception, for the condition when column bin 4 is enabled (r0x0d[3:2] or r0x0e[3:2] = 2). for this case, the value for digital tile coordinate x?direction must be doubled. the formula for digital gain setting is: digital gain = bits[3:0] x 0.25 (eq 18)
mt9v024_dsrev. g pub. 4/15 en 35 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description figure 27: tiled sample y 0/5 y 1 /5 y 2/5 y 3/5 y 4/5 y 5/5 x0_y0 x 1 _y0 x4_y0 x0_y 1 x 1 _y 1 x4_y 1 x0_y2 x 1 _y2 x4_y2 x0_y3 x 1 _y3 x4_y3 x0_y4 x 1 _y4 x4_y4 x 0/5 x 1 /5 x 2/5 x 3/5 x 4/5 x 5/5
mt9v024_dsrev. g pub. 4/15 en 36 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description black level calibration black level calibration is controlled by: ?frame dark average: r0x42 ? dark average thresholds: r0x46 ? black level calibration control: r0x47 ? black level calibration value: r0x48 ? black level calibration value step size: r0x4c the mt9v024 has automatic black level calibration on-chip, and if enabled, its result may be used in the offset correction shown in figure 28. figure 28: black level calibration flow chart the automatic black level calibration measures the average value of pixels from 2 dark rows (1 dark row if row bin 4 is enabled) of the chip. (the pixels are averaged as if they were light-sensitive and passed through the appropriate gain.) this row average is then digitally low-pass fi ltered over many frames (r0x47, bits 7:5) to remove temporal noise and random instabil ities associated with this measurement. then, the new filtered average is compar ed to a minimum acceptable level, low threshold, and a maximum accept able level, high threshold. if the average is lower than the minimum acce ptable level, the offset correction voltage is increased by a programmable offset lsb in r0x4c. (default step size is 2 lsb offset = 1 adc lsb at analog gain = 1x.) if it is above the maximum level, the offset correction voltage is decreased by 2 lsb (default). to avoid oscillation of the black level from below to above, the region the thresholds should be programmed so the difference is at least two times the offset dac step size. in normal operation, the black level calibration value/offset correction value is calcu- lated at the beginning of each frame and can be read through the two-wire serial inter- face from r0x48. this register is an 8-bit signed two?s complement value. however, if r0x47, bit 0 is set to ?1,? the cali bration value in r0x48 is used rather than the automatic black level calculation result. this feature can be used in conjunction with the ?show dark rows? feature (r0x0d[6]) if using an external black level calibration circuit. pixel o u t pu t ( r eset m i nu s si gna l) offset co rr ectio n volt ag e (r0x 48 o r r es u lt of b lc) 1 0 ( 1 2) bit adc adc d a t a (9:0) g a i n selectio n (r0x 3 5 o r r0x 3 6 o r r es u lt of agc) v ref (r0x2c) c2 c 1
mt9v024_dsrev. g pub. 4/15 en 37 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description the offset correction voltage is generated according to the following formulas: offset correction voltage = (8-b it signed two?s complement calibration value, ? 127 to 127) 0.25mv (eq 19) adc input voltage = (pixel output voltage) * analog gain + offset correction voltage (analog gain + 1) (eq 20) defective pixel correction defective pixel correction is intended to co mpensate for defective pixels by replacing their value with a value based on the surrounding pixels, making the defect less notice- able to the human eye. the locations of defective pixels are stored in a rom on chip during the manufacturing process; the maxi mum number of defects stored is 32. there is no provision for later augmenting the ta ble of programmed defects. in the defect correction block, bad pixels will be substituted by either the average of its neighboring pixels, or its nearest-neighbor pi xel, depending on pixel location. defective pixel correction is enabled by r0x07[9]. by default, correction is enabled, and pixels mapped in internal rom are replaced with corrected values. this might be unac- ceptable to some applications, in which case pixel correction should be disabled (r0x07[9] = 0). for complete details on using defective pixel correction, re fer to tn-09-250, ?defective pixel correction - description and usage?. row-wise noise correction row-wise noise correction is controlled by the following registers: ?r0x70 row noise control ?r0x72 row noise constant row-wise noise cancellation is performed by calculating a row average from a set of opti- cally black pixels at the start of each row and then applying each average to all the active pixels of the row. read dark columns register bit and row noise correction enable register bit must both be set to enable row- wise noise cancellation to be performed. the behavior when read dark columns register bit = 0 and row noise correction enable register bit = 1 is undefined. the algorithm works as follows: logical columns 755-790 in the pixel array prov ide 36 optically black pixel values. of the 36 values, two smallest value and two largest values are discarded. the remaining 32 values are averaged by summing them and disc arding the 5 lsb of the result. the 10-bit result is subtracted from each pixel value on the row in turn. in addition, a positive constant will be added (reg0x71, bits 7:0). this constant should be set to the dark level targeted by the black level algorithm plus the noise expected on the measurements of the averaged values from dark columns; it is meant to prevent clipping from negative noise fluctuations. pixel value = adc value ? dark column average + r0x71[9:0] (eq 21) note that this algorithm does not work in color sensor.
mt9v024_dsrev. g pub. 4/15 en 38 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description automatic gain control and automatic exposure control the integrated aec/agc unit is responsible fo r ensuring that optimal auto settings of exposure and (analog) gain are computed and updated every frame. aec and agc can be individually enabled or disabled by r0xaf. when aec is disabled (r0xaf[0] = 0), the sensor uses the manual exposure value in coarse and fine shutter width registers. when agc is disabled (r0xaf [1] = 0), the sensor uses the manual gain value in r0x35 or r0x36. see ?pixel integrat ion control? on page 24 for more informa- tion. figure 29: controllable and observable aec/agc registers the exposure is measured in row-time by reading r0xbb. the exposure range is 1 to 2047. the gain is measured in gain-units by reading r0xba. the gain range is 16 to 63 (unity gain = 16 gain-units; multiply by 1/16 to get the true gain). when aec is enabled (r0xaf), the maximum auto exposure value is limited by r0xbd; minimum auto exposure is limited by aec minimum exposure, r0xac. note: aec does not support sub-row timing; calcul ated exposure values are rounded down to the nearest row-time. for smoother response, manual control is recommended for short exposure times. when agc is enabled (r0xaf), the maximum auto gain value is limited by r0xab; minimum auto gain is fixed to 16 gain-units. the exposure control measures current scene luminosity and desired output luminosity by accumulating a histogram of pixel values while reading out a frame. all pixels are used, whether in color or mono mode. the desired exposure and gain are then calcu- lated from this for subsequent frame. when binning is enabled, tuning of the aec may be required. the histogram pixel count register, r0xb0, may be adjusted to reflect reduced pixel count. desired bin register, r0xa5, may be adjusted as required. exp. lpf (r0xa 8 ) 1 0 1 0 exp. skip (r0xa6) co ar se sh u tte r wi d th tot a l aec ena b le (r0xaf[0 o r 8 ]) max. exposure (r0x b d) min exposure (r0xac) aec unit to ex p os ur e ti m i ng co n t r ol aec output r0x bb r0x b a to ana lo g ga i n co n t r ol histogram generator unit agc unit gain lpf (r0xa b ) gain skip (r0xa9) manual gain a o r b agc ena b le (r0xaf[ 1 o r 9]) agc output max. gain (r0xa b ) min gain desired b in ( d esi r e d l um i nan ce) (r0xa5) current b in (c urr e n t l um i nan ce) (r0x b c) 1 6
mt9v024_dsrev. g pub. 4/15 en 39 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description pixel clock speed the pixel clock speed is same as the master clock (sysclk) at 26.66 mhz by default. however, when column binning 2 or 4 (r0x0d or r0x0e, bit 2 or 3) is enabled, the pixel clock speed is reduced by half and one-fourth of the master clock speed respectively. see ?read mode options? on page 36 and ?column binning? on page 37 for additional infor- mation. hard reset of logic the rc circuit for the mt9v024 uses a 10k ?? resistor and a 0.1 f capacitor. the rise time for the rc circuit is 1 s maximum. soft reset of logic soft reset of logic is controlled by: ?r0x0c reset bit 0 is used to reset the digital logic of the sensor while preserving the existing two-wire serial interface configuration. furthermore, by asserting the soft reset, the sensor aborts the current frame it is processing and star ts a new frame. bit 1 is a shadowed reset control register bit to explicitly reset the automatic gain and exposure control feature. these two bits are self-resetting bits and also return to ?0? during two-wire serial inter- face reads. standby control the sensor goes into standby mode by setting standby to high. once the sensor detects that standby is asserted, it comple tes the current frame before disabling the digital logic, internal clocks, and analog power enable signal. to release the sensor out from the standby mode, reset standby back to low. the lvds must be powered to ensure that the device is in standby mode. see "appendix a: power-on reset and standby timing" on page 54 for more information on standby. monitor mode control monitor mode is controlled by: ? r0xd9 monitor mode enable ? r0xc0 monitor mode image capture control the sensor goes into monitor mode when r0xd9[0] is set to high. in this mode, the sensor first captures a programmable number of frames (r0xc0), then goes into a sleep period for five minutes. the cycle of sleeping for five minutes and waking up to capture a number of frames continues until r0xd9[0] is cleared to return to normal operation. in some applications when monitor mode is enabled, the purpose of capturing frames is to calibrate the gain and exposure of the scene using automatic gain and exposure control feature. this feature typically takes less than 10 frames to settle. in case a larger number of frames is needed, the value of r0xc0 may be increased to capture more frames. during the sleep period, none of the analog ci rcuitry and a very small fraction of digital logic (including a five-minute timer) is powered. the master clock (sysclk) is therefore always required.
mt9v024_dsrev. g pub. 4/15 en 40 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description read mode options (also see ?output data format? on page 8 and ?output data timing? on page 9.) column flip by setting bit 5 of r0x0d or r0x0e the readou t order of the columns is reversed, as shown in figure 30 on page 36. row flip by setting bit 4 of r0x0d or r0x0e the readout order of the rows is reversed, as shown in figure 31. figure 30: readout of six pixels in normal and column flip output mode figure 31: readout of six rows in normal and row flip output mode pixel binning in addition to windowing mode in which smaller resolutions (cif, qcif) are obtained by selecting a smaller window from the sensor array, the mt9v024 also provides the ability to down-sample the entire image captured by the pixel array using pixel binning. there are two resolution options: binning 2 and binning 4, which reduce resolution by two or by four, respectively. row and column binning are separately selected. image mirroring options will work in conjunction with binning. for column binning, either two or four columns are combined by averaging to create the resulting column. for row binning, the binning result value depends on the difference in pixel values: for pixel signal differences of le ss than 200 lsbs, the result is the average of the pixel values. for pixel differences of greater than 200 lsbs, the result is the value of the darker pixel value. line_valid no rma l r e ad o u t d out (9:0) reve r se r e ad o u t d out (9:0) p 4 , 1 (9:0) p 4 , n (9:0) p 4 , n - 1 (9:0) p 4 , n -2 (9:0) p 4 , n - 3 (9:0) p 4 , n - 4 (9:0) p 4 , n -5 (9:0) p 4 ,2 (9:0) p 4 , 3 (9:0) p 4 , 4 (9:0) p 4 ,5 (9:0) p 4 ,6 (9:0) frame_valid normal readout d out (9:0) reverse readout d out (9:0) row4 (9:0) row5 (9:0) row6 (9:0) row7 (9:0) row8 7(9:0) row9 (9:0) row9 (9:0) row8 (9:0) row7 (9:0) row6 (9:0) row5 7(9:0) row4 (9:0)
mt9v024_dsrev. g pub. 4/15 en 41 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description binning operation increases snr but decreases resolution. enabling row bin2 and row bin4 improves frame rate by 2x and 4x respectively. column binning does not increase the frame rate. row binning by setting bit 0 or 1 of r0x0d or r0x0e, only ha lf or one-fourth of the row set is read out, as shown in figure 32. the number of rows read out is half or one-fourth of the value set in r0x03. the row binning result depends on the difference in pixel values: for pixel signal differences less than 200 lsbs, the result is the average of the pixel values. for pixel differences of 200 lsbs or more, the result is the value of the darker pixel value. column binning for column binning, either two or four columns are combined by averaging to create the result. in setting bit 2 or 3 of r0x0d or r0x0 e, the pixel data rate is slowed down by a factor of either two or four, respectively. this is due to the overhead time in the digital pixel data processing chain. as a result, the pixel clock speed is also reduced accordingly. figure 32: readout of 8 pixels in normal and row bin output mode line_valid no rma l r e ad o u t d out (9:0) row 4 (9:0) row5 (9:0) row6 (9:0) row7 (9:0) row 8 (9:0) row9 (9:0) row 1 0 (9:0) row 11 (9:0) line_valid row b i n 2 r e ad o u t d out (9:0) row 4 (9:0) row6 (9:0) row 8 (9:0) line_valid row b i n 4 r e ad o u t d out (9:0) row 4 (9:0) row 8 (9:0) row 1 0 (9:0)
mt9v024_dsrev. g pub. 4/15 en 42 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description figure 33: readout of 8 pixels in normal and column bin output mode interlaced readout the mt9v024 has two interlaced readout options. by setting r0x07[2:0] = 1, all the even- numbered rows are read out first, followed by a number of programmable field blanking rows (set by r0xbf[7:0]), then the odd-numbered rows, and finally the vertical blanking rows. by setting r0x07[2:0] = 2 only one field row is read out. consequently, the number of rows read out is half what is set in the window height register. the row start register determines wh ich field gets read out; if the row start register is even, then the even field is read out; if row start address is odd, then the odd field is read out. line_valid normal readout d out (9:0) pixclk d out (9:0) pixclk d out (9:0) pixclk d1 (9:0) d2 (9:0) d3 (9:0) d4 (9:0) d5 (9:0) d6 (9:0) d7 (9:0) d8 (9:0) line_valid column bin 2 readout d1 (9:0) d3 (9:0) d5 (9:0) d7 (9:0) line_valid column bin 4 readout d out (9:0) d1 (9:0) d5 (9:0)
mt9v024_dsrev. g pub. 4/15 en 43 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description figure 34: spatial illustration of interlaced image readout when interlaced mode is enabled, the total number of blanking rows are determined by both field blanking register (r0xbf) and vert ical blanking register (r0x06 or r0xce). the followings are their equations. field blanking = r0xbf[7:0] (eq 22) vertical blanking = r0x06[8:0] ? r0xbf[7:0] (context a) or r0xce[8:0] ? r0xbf[7:0] (context b) (eq 23) with minimum vertical blanking requirement = 4 (absolute minimum to operate; see vertical blanking registers description for vblank minimums for valid image output) (eq 24) similar to progressive scan, fv is logic low during the valid image row only. binning should not be used in conjunction with interlaced mode. p 4 , 1 p 4 ,2 p 4 , 3 .....................................p 4 , n - 1 p 4 , n p 6,0 p 6, 1 p 6,2 .....................................p 6, n - 1 p 6, n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m -2,0 p m -2,2 .....................................p m -2, n -2 p m -2, n p m ,2 p m ,2 .....................................p m , n - 1 p m , n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ............................................................................................. 00 00 00 00 00 00 ............................................................................................. 00 00 00 valid image - eve n fiel d horizontal b lanking vertical b lanking p 5, 1 p 5,2 p 5, 3 .....................................p 5, n - 1 p 5, n p 7,0 p 7, 1 p 7,2 .....................................p 7, n - 1 p 7, n p m - 3 , 1 p m - 3 ,2 .....................................p m - 3 , n - 1 p m - 3 , n p m , 1 p m , 1 .....................................p m , n - 1 p m , n valid image - o dd fiel d field b lanking
mt9v024_dsrev. g pub. 4/15 en 44 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description line_valid by setting bit 2 and 3 of r0x72, the lv signal can get three different output formats. the formats for reading out four rows and two vert ical blanking rows are shown in figure 35. in the last format, the lv signal is the xor between the continuous lv signal and the fv signal. figure 35: different line_valid formats lvds serial (stand-alone/stereo) output the lvds interface allows for the streaming of sensor data serially to a standard off-the- shelf deserializer up to eight meters away fr om the sensor. the pixels (and controls) are packeted?12-bit packets for stand-alone mode and 18-bit packets for stereoscopy mode. all serial signaling (clk and data) is lv ds. the lvds serial output could either be data from a single sensor (stand-alone) or stream-merged data fr om two sensors (self and its stereoscopic slave pair). the appendic es describe in detail the topologies for both stand-alone and stereoscopic modes. there are two standard deserializers that can be used. one for a stand-alone sensor stream and the other from a stereoscopic st ream. the deserializer attached to a stand- alone sensor is able to reproduce the standard parallel output (8-bit pixel data, lv, fv, and pixclk). the deserializer attached to a stereoscopic sensor is able to reproduce 8- bit pixel data from each sensor (with embedded lv and fv) and pixel-clk. an additional (simple) piece of logic is required to extract lv and fv from the 8-bit pixel data. irrespec- tive of the mode (stereoscopy/stand-alone), lv and fv are always embedded in the pixel data. in stereoscopic mode, the two sensors run in lock-step, implying all state machines are in the same state at any given time. this is ensured by the sensor-pair getting their sys- clks and sys-resets in the same instance. configuration writes through the two-wire serial interface are done in such a way th at both sensors can get their configuration updates at once. the inter-sensor serial link is designed in such a way that once the slave pll locks and the data-dly, shft-clk-dly and stream-latency-sel are configured, the master sensor streams valid stereo content ir respective of any variation voltage and/or temperature as long as it is within specification. the configuration values of data-dly, shft-clk-dly and stream-latency-sel are either predetermined from the board-layout or can be empirically determined by reading back the stereo-error flag. this flag is asserted when the two sensor streams are not in sync when merged. the combo_reg is used for out-of-sync diagnosis. def au lt frame_valid line_valid co n ti nu o u sly frame_valid line_valid xor frame_valid line_valid
mt9v024_dsrev. g pub. 4/15 en 45 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description figure 36: serial output format for a 6x2 frame notes: 1. external pixel values of 0, 1, 2, 3, are reserved (they only convey control information). any raw pixel of value 0, 1, 2 and 3 will be substituted with 4. 2. the external pixel sequence 1023, 0, 1023 is a reserved sequence (conveys control information for legacy support of mt9v021 applications). any raw pi xel sequence of 1023, 0, 1023 will be substi- tuted with an output serial stream of 1023, 4, 1023. lvds output format in stand-alone mode, the packet size is 12 bits (2 frame bits and 10 payload bits); 10-bit pixels or 8-bit pixels can be selected. in 8-bit pixel mode (r0xb6[0] = 0), the packet consists of a start bit, 8-bit pixel data (with sync codes), the line valid bit, the frame valid bit and the stop bit. for 10-bit pixel mode (r0xb6[0] = 1), th e packet consists of a start bit, 10-bit pixel data, and the stop bit. in stereoscopic mode, the packet size is 18 bits (2 frame bits and 16 payload bits). the packet consists of a start bit, the master pixe l byte (with sync codes), the slave byte (with sync codes), and the stop bit.) table 7: lvds packet format in stand-alone mode (stereoscopy mode bit de-asserted) 12-bit packet use_10-bit_pixels bit de- asserted (8-bit mode) use_10-bit_pixels bit asserted (10-bit mode) bit[0] 1'b1 (start bit) 1'b1 (start bit) bit[1] pixeldata[2] pixeldata[0] bit2] pixeldata[3] pixeldata[1] bit[3] pixeldata[4] pixeldata[2] bit4] pixeldata[5] pixeldata[3] bit[5] pixeldata[6] pixeldata[4] bit[6] pixeldata[7] pixeldata[5] bit[7] pixeldata[8] pixeldata[6] bit[8] pixeldata[9] pixeldata[7] bit[9] line_valid pixeldata[8] bit[10] frame_valid pixeldata[9] bit[11] 1'b0 (stop bit) 1'b0 (stop bit) i n te rna l pixclk i n te rna l p ara llel d a t a i n te rna l li n e_v a li d i n te rna l f ram e_v a li d exte rna l se r i a l d a t a o u t p 41 p 43 p 4 2 p 44 p 4 5 p 4 6 p 5 4 p 55 p 56 p 52 p 5 1 p 5 3 1 02 31 02 3 0 1 p 41 p 4 2 p 4 6 2 1 p 44 p 43 p 4 5 p 5 1 p 52 p 56 2 p 5 4 p 5 3 p 55 3
mt9v024_dsrev. g pub. 4/15 en 46 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description control signals lv and fv can be reconstr ucted from their respective preceding and succeeding flags that are always embedded within the pixel data in the form of reserved words. when lvds mode is enabled along with column binning (bin 2 or bin 4, r0x0d[3:2]), the packet size remains the same but the serial pi xel data stream repeats itself depending on whether 2x or 4x binning is set: ? for bin 2, lvds outputs double the expected data (post-binning pixel 0,0 is output twice in sequence, followed by pixel 0,1 twice, . . .). ? for bin 4, lvds outputs 4 times the expected data (pixel 0,0 is output 4 times in sequence followed by pixel 0,1 times 4, . . .). the receiving hardware will need to undersample the output stream,getting data either every 2 clocks (bin 2) or every 4 (bin 4) clocks. if the sensor provides a pixel whose value is 0,1, 2, or 3 (that is, the same as a reserved word) then the outgoing serial pixel value is switched to 4. table 8: lvds packet format in stereosc opy mode (stereoscopy mode bit asserted) 18-bit packet function bit[0] 1'b1 (start bit) bit[1] mastersensorpixeldata[2] bit[2] mastersensorpixeldata[3] bit[3] mastersensorpixeldata[4] bit[4] mastersensorpixeldata[5] bit[5] mastersensorpixeldata[6] bit[6] mastersensorpixeldata[7] bit[7] mastersensorpixeldata[8] bit[8] mastersensorpixeldata[9] bit[9] slavesensorpixeldata[2] bit[10] slavesensorpixeldata[3] bit[11] slavesensorpixeldata[4] bit[12] slavesensorpixeldata[5] bit[13] slavesensorpixeldata[6] bit[14] slavesensorpixeldata[7] bit[15] slavesensorpixeldata[8] bit[16] slavesensorpixeldata[9] bit[17] 1'b0 (stop bit) table 9: reserved words in the pixel data stream pixel data reserved word flag 0 precedes frame valid assertion 1 precedes line valid assertion 2 succeeds line valid de-assertion 3 succeeds frame valid de-assertion
mt9v024_dsrev. g pub. 4/15 en 47 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description lvds enable and disable the table 10 and table 11 further explain the state of the lvds output pins depending on lvds control settings. when the lvds block is not used, it may be left powered down to reduce power consumption. note: error pin: when the sensor is not in stereo mode, the error pin is at low. table 10: ser_dataout_* state r0xb1[1] lvds power down r0xb3[4] lvds data power down ser_dataout_* 0 0 active 0 1 active 10 z 11 z table 11: shft_clk_* state r0xb1[1] lvds power down r0xb2[4] lvds shift-clk power down shft_clkout_* 00active 01 z 10 z 11 z
mt9v024_dsrev. g pub. 4/15 en 48 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor feature description lvds data bus timing the lvds bus timing waveforms and timing specifications are shown in table 12 and figure 37. figure 37: lvds timing table 12: lvds ac timing specifications v pwr = 3.3v 0.3v; t j = C 40c to +105c; output load = 100 ? ; frequency 27 mhz parameter minimum typical maximum unit lvds clock rise time C 0.22 0.30 ns lvds clock fall time C 0.22 0.30 ns lvds data rise time C 0.28 0.30 ns lvds data fall time C 0.28 0.30 ns lvds data setup time 0.3 0.67 C ns lvds data hold time 0.1 1.34 C ns lvds clock jitter C 92 ps d a t a rise/f a ll ti m e ( 1 0% - 90%) d a t a set up ti m e d a t a hol d ti m e lvds d a t a o u t pu t (ser_dataout_n/p) lvds clock o u t pu t (shft_clkout_n/p) clock rise/f a ll ti m e ( 1 0% - 90%) clock jitte r
mt9v024_dsrev. g pub. 4/15 en 49 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor electrical specifications electrical specifications table 13: dc electrical characteristics over temperature v pwr = 3.3v 0.3v; t j = C 40c to +105 c; output load = 10pf; frequency 13 mhz to 27 mhz; lvds off symbol definition condition minimum typical maximum unit v ih input high voltage v pwr - 1.4 C v v il input low voltage C 1.3 v i in input leakage current no pull-up resistor; v in = v pwr or v gnd -5 C 5 ? a v oh output high voltage i oh = C4.0ma v pwr - 0.3 C C v v ol output low voltage i ol = 4.0ma C C 0.3 v i oh output high current v oh = v dd - 0.7 -11 C C ma i ol output low current v ol = 0.7 C C 11 ma i pwr a analog supply current default settings C 12 20 ma i pix pixel supply current default settings C 1.1 3 ma i pwr d digital supply current default settings, c load = 10pf C 42 60 ma i lvds lvds supply current default settings with lvds on C 13 16 ma i pwr a standby analog standby supply current stdby = v dd C0.23 ? a i pwr d standby clock off digital standby supply current with clock off stdby = v dd , clkin = 0 mhz C0.110 ? a i pwr d standby clock on digital standby supply current with clock on stdby= v dd , clkin = 27 mhz C12ma table 14: dc electrical characteristics v pwr = 3.3v 0.3v; t a = ambient = 25 c symbol definition condition minimum typical maximum unit lvds driver dc specifications |v od | output differential voltage r load = 100 ?? 1 % 250 C 400 mv |dv od | change in v od between complementary output states CC50mv v os output offset voltage 1.0 1.2 1.4 v dv os pixel array current CC35mv i os digital supply current ? 10 ma i o z output current when driver is tri- state ? 1 ? a lvds receiver dc specifications v idth + input differential | v gpd | < 925mv C100 C 100 mv iin input current C C ? 20 ? a
mt9v024_dsrev. g pub. 4/15 en 50 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor electrical specifications notes: 1. this is a stress rating only, and functional op eration of the device at these or any other conditions above those indicated in the operational sect ions of this specific ation is not implied. exposure to absolute maximum rating cond itions for extended periods may affect reliability. table 15: absolute maximum ratings caution stresses greater than those listed may cause permanent damage to the device. symbol parameter minimum maximum unit v supply power supply voltage (all supplies) C0.3 4.5 v i supply total power supply current C 200 ma i gnd total ground current C 200 ma v in dc input voltage C0.3 v dd + 0.3 v v out dc output voltage C0.3 v dd + 0.3 v t stg 1 storage temperature C50 +150 c table 16: ac electrical characteristics v pwr = 3.3v 0.3v; t j =C40 c to +105 c; output load = 10pf symbol definition condition minimum typical maximum unit sysclk input clock frequency 13.0 26.6 27.0 mhz clock duty cycle 45.0 50.0 55.0 % t r input clock rise time C 3 5 ns t f input clock fall time C 3 5 ns t plh p sysclk to pixclk propagation delay c load = 10pf 4 6 8 ns t pd pixclk to valid d out (9:0) propagation delay c load = 10pf C3 0.6 3 ns t sd data setup time 14 16 C ns t hd data hold time 14 16 C t pflr pixclk to lv propagation delay c load = 10pf 5 7 9 ns t pflf pixclk to fv propagation delay c load = 10pf 5 7 9 ns
mt9v024_dsrev. g pub. 4/15 en 51 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor electrical specifications propagation delays for pixc lk and data out signals the pixel clock is inverted and delayed relative to the master clock. the relative delay from the master clock (sysclk) rising edge to both the pixel clock (pixclk) falling edge and the data output transition is typically 7n s. note that the falling edge of the pixel clock occurs at approximately the same time as the data ou tput transitions. see table 16 on page 46 for data setup and hold times. figure 38: propagation delays for pixclk and data out signals propagation delays for frame_valid and line_valid signals the lv and fv signals change on the same ri sing master clock edge as the data output. the lv goes high on the same rising master clock edge as the output of the first valid pixel's data and returns low on the same ma ster clock rising edge as the end of the output of the last valid pixel's data. as shown in the ?output data timing? on page 9, fv goes high 143 pixel clocks before the first lv goes high. it returns low 23 pixel clocks after the last lv goes low. figure 39: propagation delays for frame_valid and line_valid signals t pd t r t f t plh p t hd t sd sysclk pixclk d out (9:0) pixclk frame_valid line_valid t p flf t p flr pixclk frame_valid line_valid
mt9v024_dsrev. g pub. 4/15 en 52 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor electrical specifications two-wire serial bus timing detailed timing waveforms and parameters for the two-wire serial interface bus are shown in figure 40 and table 17. figure 40: two-wire serial bus timing parameters notes: 1. this table is based on i 2 c standard (v2.1 january 2000). philips semiconductor. 2. two-wire control is i 2 c-compatible. 3. all values referred to v ihmin = 0.9 v dd and v ilmax = 0.1v dd levels. sensor exclk = 27 mhz. 4. a device must internally provide a hold time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 5. the maximum t hd;dat has only to be met if the device does not stretch the low period (t low ) of the s clk signal. table 17: two-wire seri al bus characteristics f extclk = 27 mhz; v dd = 1.8v; v dd _io = 2.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _dac = 2.8v; t a = 25c parameter symbol standard-mode fast-mode unit min max min max s clk clock frequency f scl 0 100 0 400 khz after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - ? s low period of the sclk clock t low 4.7 - 1.3 - ? s high period of the sclk clock t high 4.0 - 0.6 - ? s set-up time for a repeated start condition t su;sta 4.7 - 0.6 - ? s data hold time: t hd;dat 0 4 3.45 5 0 6 0.9 5 ? s data set-up time t su;dat 250 - 100 6 -ns rise time of both s data and s clk signals t r - 1000 20 + 0.1cb 7 300 ns fall time of both s data and s clk signals t f - 300 20 + 0.1cb 7 300 ns set-up time for stop condition t su;sto 4.0 - 0.6 - ? s bus free time between a stop and start condition t buf 4.7 - 1.3 - ? s capacitive load for each bus line cb - 400 - 400 pf serial interface input pin capacitance c in_si - 3.3 - 3.3 pf s data max load capacitance c load_sd -30-30pf s data pull-up resistor rsd 1.5 4.7 1.5 4.7 k ? s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f s data s clk p s t buf t r t f t r t hd;sta
mt9v024_dsrev. g pub. 4/15 en 53 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor electrical specifications 6. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automati cally be the case if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the s clk line is released. 7. cb = total capacitance of one bus line in pf. minimum master clock cycles in addition to the ac timing requirements described in table 17 on page 48, the two-wire serial bus operation also requir es certain minimum master clock cycles between transitions. these are specified in figures 41 through 46, in units of master clock cycles. figure 41: serial host interface start condition timing figure 42: serial host interface stop condition timing note: all timing are in units of master clock cycle. figure 43: serial host interface data timing for write note: s data is driven by an off-chip transmitter. sclk 4 s data 4 sclk 4 s data 4 sclk 4 s data 4
mt9v024_dsrev. g pub. 4/15 en 54 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor electrical specifications figure 44: serial host interface data timing for read note: s data is pulled low by the sensor, or allowed to be pulled high by a pull-up resistor off-chip. figure 45: acknowledge signal timing after an 8-bit write to the sensor figure 46: acknowledge signal timing after an 8-bit read from the sensor note: after a read, the master receiver must pull down s data to acknowledge receipt of data bits. when the read sequence is complete, the master must generate a no acknowledge by leaving s data to float high. on the following cycle, a start or stop bit may be used. sclk 5 s data sclk se n so r pu lls d ow n s data p i n 6 s data 3 n so r t r i-st a tes s data p i n (t urn s off pu ll d ow n ) 7 s data 6
mt9v024: 1/3-inch wide-vga digital image sensor electrical specifications mt9v024_dsrev. g pub. 4/15 en 55 ?semiconductor components industries, llc, 2015. figure 47: typical quantum efficiency ? rgb bayer figure 48: typical quantum efficiency ? monochrome
mt9v024_dsrev. g pub. 4/15 en 56 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor electrical specifications figure 49: typical quantum efficiencyrccc
mt9v024_dsrev. g pub. 4/15 en 57 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor package dimensions package dimensions figure 50: 52-ball ibga note: all dimensions in millimeters. seating plane 9 0.075 3.5 optical area optical center 0.4 (for reference only) 0.9 (for reference only) 5.5 first active pixel fuses 7 1.849 1.999 4.9 1 typ 1 typ 8 7 6 5 4 3 2 1 a b c d e f g h 9 0.075 0.375 0.05 0.525 0.05 0.125 (for r eference only) c l c l 7 3.5 0.1 a a d c b ball a1 id 52x ?0.55 dimensions apply to solder balls post reflow. the pre- reflow ball is ?0.5 on a ?0.4 nsmd ball pad. encapsulant: epoxy image sensor die lid material: borosilica te glass 0.4 thickness substrate material: plastic lamina te solder ball ma terial: sac305 (96.5 % sn, 3 % ag , 0.5 % cu) maximum rota tion of optical area rela tive to package edges: 1o maximum tilt of optical area rela tive to package edge : 25 microns maximum tilt of optical area rela tive to top of cover glass: 50 micr ons d 2.88 ctr 4.512 ctr ?0.15 a b c ?0.15 a c b
mt9v024_dsrev. g pub. 4/15 en 58 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor appendix a: power-on reset and standby timing appendix a: power-on reset and standby timing there are no constraints concerning the or der in which the various power supplies are applied; however, the mt9v024 requires reset to operate properly at power-up. refer to figure 51 for the power-up, reset, and standby sequences. figure 51: power-up, reset, clock, and standby sequence notes: 1. all output signals are defi ned during initial power-up with reset_bar held low without sysclk being active. to properly reset the rest of the sens or, during initial power-up, assert reset_bar (set to low state) for at least 750ns after all power su pplies have stabilized and sysclk is active (being clocked). driving reset_bar to low state do es not put the part in a low power state. 2. before using two-wire serial interface, wait for 10 sysclk rising edges after reset_bar is de- asserted. 3. once the sensor detects that standby has been asserted, it completes the current frame readout before entering standby mode. the user must su pply enough sysclks to allow a complete frame readout. see table 2, frame time, on page 9 for more information. 4. in standby, all video data and synchronization output signals are driven to a low state. 5. in standby, the two-wire serial interface is not active. sysclk two-wire serial i/f sclk , s data reset_bar v dd , v dd lvds, v aa , vaapix data output standby min 10 sysclk cycles pre-standby standby wake up active driven = 0 low-power non-low-power does not respond to serial interface when standby = 1 d out [9:0] power up non-low-power min 20 sysclk cycles min 10 sysclk cycles active power down d out [9:0] driven = 0 note 3 min 10 sysclk cycles
mt9v024_dsrev. g pub. 4/15 en 59 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor appendix b: electrical identification of cfa type appendix b: electrical identification of cfa type in order to identify the cfa type (rgb bayer, monochrome, rccc) that a specific mt9v024 has been, the following table may be used. cfa r0x6b[11:9] r0x6b[8:0] rgb 6 4 rccc 5 4 mono 0 4
mt9v024_dsrev. g pub. 4/15 en 60 ?semiconductor components industries, llc, 2015. mt9v024: 1/3-inch wide-vga digital image sensor revision history revision history rev.g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/16/15 ? updated ?ordering information? on page 2 rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/27/15 ? converted to on semiconductor template ? removed confidential marking rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/20/12 ? updated title of figure 5: ?pixel color pattern detail rgb bayer (top right corner),? on page 6 ? updated title of ?color (rgb baye r) device limitations? on page 7 ? moved ?recommended register settings? to follow ?real-time context switching? on page 16 ? updated figure 14: ?simultaneous master mode synchronization waveforms #1,? on page 18 ? updated figure 15: ?simultaneous master mode synchronization waveforms #2,? on page 19 ? updated figure 16: ?sequential master mode synchronization waveforms,? on page 19 ? updated figure 18: ?snapshot mode frame synchronization waveforms,? on page 20 ? added sentence after fifth paragraph of ?slave mode? on page 20 ? replaced figure 19: ?slave mode operation? with figure 19: ?exposure and readout timing (simultaneous mode),? on page 21 and figure 20: ?exposure and readout timing (sequential mode),? on page 22 ? deleted figure 23: ?latency when changing integration,? on page 31 ? updated unit symbols in table 17, ?two-wire serial bus characteristics,? on page 48 ? added ?appendix b: electrical iden tification of cfa type? on page 55 rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/4/12 ? updated ?features? on page 1 ? updated table 1, ?key performance parameters,? on page 1 ? updated table 2, ?available part numbers,? on page 1 ? added figure 6: ?pixel color pattern detail rccc,? on page 6 ? updated note for table 3, ?frame time?long integration time,? on page 10 ? added ?serial bus description? on page 11 ? updated ?real-time context switching? on page 16 ? updated figure 23: ?latency when changing integration,? on page 31 ? updated figure 25: ?12- to 10-bit companding chart,? on page 28 ? updated ?changes to gain settings? on page 29 ? updated figure 26: ?latency of gain register(s) in master mode,? on page 29 ? updated equation 19 and equation 20 on page 33 ? updated figure 31: ?readout of six rows in normal and row flip output mode,? on page 36 ? updated figure 33: ?readout of 8 pixels in normal and column bin output mode,? on page 38 ? updated ?digital gain? on page 30 ? updated figure 40: ?two-wire serial bus timing parameters,? on page 48 ? updated table 17, ?two-wire serial bus characteristics,? on page 48
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. mt9v024: 1/3-inch wide-vga digital image sensor revision history mt9v024_dsrev. g pub. 4/15 en 61 ?semiconductor components industries, llc, 2015 . ? updated figure 47: ?typical quantum efficiency?rgb bayer,? on page 51 ? updated figure 48: ?typical quantum efficiency?monochrome,? on page 51 ? added figure 48: ?rccc quantum efficiency,? on page 55 ? updated figure 51: ?power-up, reset, clock, and standby sequence,? on page 54 rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/10 ? applied updated aptina template ? updated revision history rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/10 ? updated to aptina template; register tables moved to new document, mt9v024 register reference rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/08 ?initial release

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